The 64-bit execution state of the ARMv8-A architecture. All general-purpose registers are 64 bits wide. Instruction encoding is fixed-width (32 bits).
ASID (Address Space ID)
A small identifier (8 or 16 bits) stored in the TLB to distinguish translations from different processes. Avoids TLB flushing on context switches.
Bootloader
A small program that loads the kernel from storage into memory and transfers control to it. On QEMU virt, the bootloader is built into the firmware.
Buddy Allocator
A memory allocation algorithm that splits and merges power-of-two-sized blocks. Used for physical page allocation in most kernels.
Cache Coherency
The property that all CPU cores see the same data for a given memory address. Ensured by hardware cache-coherent interconnect (e.g., AMBA ACE or CHI).
Context Switch
The operation of saving the current process's CPU state and restoring another process's state. Performed by the scheduler.
DABORT (Data Abort)
An exception triggered by a failed data access (load or store). Causes include page faults, permission violations, and alignment errors.
DMA (Direct Memory Access)
A feature that allows hardware devices to read and write memory directly without CPU involvement. Improves I/O performance.
EL0, EL1, EL2, EL3
ARM64 exception levels. EL0 is user space, EL1 is kernel, EL2 is hypervisor, EL3 is secure monitor. Higher numbers have more privilege.
ELF (Executable and Linkable Format)
The standard binary format for executables, object files, and shared libraries on Unix-like systems. Chapter 37 covers ELF loading in detail.
ERET
The ARM64 instruction that returns from an exception. It restores the PC from ELR_EL1 and the processor state from SPSR_EL1.
Exception Level
A privilege level in ARM64. Higher exception levels have more privileges and can access registers that lower levels cannot.
FDT (Flattened Device Tree)
A data structure describing hardware. Passed by the bootloader to the kernel. The kernel parses it to discover devices, memory layout, and configuration.
Frame Pointer (x29)
A register that points to the current function's stack frame. Used for stack unwinding and debugging.
Framebuffer
A region of memory that maps directly to screen pixels. Writing pixel values to the framebuffer changes what is displayed.
GIC (Generic Interrupt Controller)
The ARM interrupt controller. GICv3 is used on QEMU virt. It manages interrupt distribution, prioritization, and routing to CPU cores.
GICD, GICR, GICC, GIC ITS
GIC interfaces: Distributor (GICD) routes interrupts, Redistributor (GICR) manages per-CPU interrupts, CPU Interface (GICC) is the CPU's view, ITS translates MSI interrupts.
IABORT (Instruction Abort)
An exception triggered by a failed instruction fetch. Usually caused by a page fault or permission violation on the code page.
IPC (Inter-Process Communication)
Mechanisms for processes to exchange data and synchronize: pipes, shared memory, message queues, and signals.
IRQ (Interrupt Request)
A hardware signal that tells the CPU an event needs attention. The CPU suspends normal execution and runs the interrupt handler.
Linker Script
A file that tells the linker how to arrange sections in the output binary. For kernels, it defines the load address, section ordering, and symbol locations.
MAIR_EL1
Memory Attribute Indirection Register. Defines the cacheability and memory type for each of the 8 AttrIdx fields in page table entries.
MMU (Memory Management Unit)
Hardware that translates virtual addresses to physical addresses on every memory access. Controlled by page tables and system registers.
Page
A fixed-size block of virtual memory. ARM64 supports 4 KB, 16 KB, and 64 KB pages. The kernel maps virtual pages to physical frames.
Page Table
A multi-level data structure in memory that maps virtual addresses to physical addresses. ARM64 uses 3 to 4 levels depending on page size and address width.
Paging
A memory management scheme that maps fixed-size virtual pages to physical frames. Eliminates external fragmentation and enables virtual memory.
PCB (Process Control Block)
A kernel data structure that stores all information about a process: register state, page table pointer, PID, state, open files, etc.
PID (Process Identifier)
A unique integer assigned to each process by the kernel.
PSCI (Power State Coordination Interface)
A firmware interface for CPU power management. Used to bring up secondary CPU cores in SMP systems.
SCTLR_EL1
System Control Register. Controls core features: MMU enable, cache enable, alignment checking, and many other CPU-wide settings.
Scheduler
The kernel component that decides which process runs next on the CPU. Implements a policy (e.g., round-robin, priority-based) to share CPU time.
SMP (Symmetric Multiprocessing)
A system with two or more identical CPU cores sharing memory. The kernel must handle synchronization, cache coherency, and per-CPU data.
SPSR_EL1 (Saved Program Status Register)
Stores the processor state (exception level, interrupt masks, condition flags) that was active before an exception occurred. Restored by ERET.
SVC (Supervisor Call)
The ARM64 instruction used by user-space programs to make system calls. Traps from EL0 to EL1.
System Call
A request from user space to the kernel for a privileged operation (open file, allocate memory, send network data). Implemented via SVC on ARM64.
TCR_EL1 (Translation Control Register)
Controls page table configuration: page size, address space size, translation table walk cacheability, and other MMU settings.
TLB (Translation Lookaside Buffer)
A fast cache in the CPU that stores recent virtual-to-physical address translations. Avoids walking page tables on every memory access.
Translation Table (Page Table)
See Page Table.
TTBR0_EL1 / TTBR1_EL1
Translation Table Base Registers. TTBR0 points to the user-space page table (EL0), TTBR1 points to the kernel page table (EL1).